1. Field of the Invention
The present invention relates to a method for designing a semiconductor integrated circuit and a method for testing the same, which make it possible to suppress physical influences such as malfunctions caused by a voltage drop owing to simultaneous power consumption and interference between signal lines during a clock operation of a large-scale integrated circuit. As a result, the integrated circuit can be tested efficiently and accurately.
2. Description of Related Art
During scan testing of a semiconductor integrated circuit, a clock is supplied to each scan line in a scan-designed circuit so as to allow a signal to propagate, thereby detecting a fault in the circuit. In other words, as shown in FIG. 25, scan flip-flops 101 to 103 constitute a scan chain on a first scan line 107, while scan flip-flops 104 to 106 constitute a scan chain on a second scan line 108. When a clock 109 is supplied, a scan operation is conducted.
As shown in FIG. 26, in general, a test pattern 113 to be input to a scan line is generated automatically from circuit diagram information 111 by a tool called an ATPG (Automatic Test Pattern Generator) 112.
In general, the same clocks are supplied to the scan lines simultaneously, so signals also are shifted on the scan lines simultaneously. As shown in FIG. 25, a clock pattern for scanning includes a shift-in for setting a signal value to be taken into the circuit, a capture for actually taking the signal value into the circuit and a shift-out for taking out the result of the signal value to the outside of the circuit. Since the scan flip-flops in the circuit are switched simultaneously as described above, a recent trend toward larger-scale and finer integrated circuits has increased power consumption of the circuit during a scan operation and occurrence of malfunctions owing to a voltage drop and interference between signal lines.
For suppressing the power consumption during the scan operation, JP 10(1998)-197603 A describes providing a clock control circuit in the circuit, thereby avoiding simultaneous supply of clocks to a plurality of scan lines. As briefly shown in FIG. 27, three scan lines 121, 122 and 123 are divided into a group A and a group B. Respective clocks 124 and 125 to be input to the groups A and B are controlled by a clock control circuit 126 so as not to be supplied simultaneously to these groups. In this manner, the power consumption is reduced.
However, in the case where the three scan lines 121, 122 and 123 are connected and the circuit of the group A and that of the group B are associated with each other as shown in this figure, an accurate result cannot be obtained unless the captures are input simultaneously. Accordingly, the clocks have to be supplied simultaneously, so that the problem of high power consumption remains.
In order to solve such a problem, JP 2001-165996 A describes a method of designing a circuit in which the scan lines 122 and 123 are not connected and the circuit of the group A and that of the group B are independent from each other as shown in FIG. 28, thereby avoiding the simultaneous performance of capture operations, thus suppressing the power consumption.
However, both of the conventional technologies described above have required circuit constraints. Furthermore, the clock control has been difficult. Thus, there have been problems for practical application.